________________________________________________________________________ ACM International Symposium on Physical Design 2014 ________________________________________________________________________ Detailed-Routing-Driven Placement Contest Call for Participation ________________________________________________________________________ Registration deadline: January 15, 2013 Web site: http://www.ispd.cc/contests/14/ispd2014_contest.html ________________________________________________________________________ YOU ARE INVITED TO PARTICIPATE! Over the past decade, the ACM International Symposium on Physical Design (ISPD) has hosted contests in relevant EDA topics including placement, routing, clock tree synthesis, and gate sizing. Many contributions from the participating academic, research and industry team contestants have greatly advanced the state of the art in these areas. Continuing this long-standing tradition, we announce the 2014 ISPD contest topic and call for your participation. The 2014 contest topic is detailed-routing-driven placement. Different from past placement contests, the metric of evaluation for the submitted placements will be based upon the quality of the corresponding detailed-routing as evaluated by a commercial detailed router. There has been a significant increase in the complexity of routing-design rules at sub-20nm nodes. This has created a new set of challenges where many of the traditional methods published for minimizing routing congestion during placement are no longer adequate. . Examples of these routability challenges for placement include the following: * Accuracy of global routing models during placement: A common placement approach is to periodically consult a global router to update estimates of the routing load. The global routing feedback frequency can greatly impact the fidelity of the routing congestion map and hence placement quality. * Logical netlist complexity and irregularity: This may include a high average number of pins per net (usually 4 or more), data-path modules in the netlist, accounting for special requirements associated with clock networks, accounting for timing objectives, etc. * Physical floorplan complexity: These challenges stem from overall placement utilization, irregular shape of the placeable area (e.g., disproportionate floorplan aspect ratios, rectilinear macro shapes, and narrow channels between large macros), boundary-pin-placement restrictions, power/ground routing resource estimation, etc. * Cell pin unreachability: Connecting wires and vias to cell pins may not be possible (i.e. causes DRC violations) where cells are placed too close to each other or due to spacing restrictions and routing congestion with associated with non-default routing rules. * Restrictions on routing layers: Several of the top routing layers may be prohibited for signal nets. Particular routing layers (typically top layers) are allocated for routing various critical net groups (e.g. clock nets, high-activity switching nets, long critical nets, power/ground nets, etc.). * Increased DRC and DFM complexity:  There are additional DRC and DFM rules on routing and implant layers for advanced process nodes (28nm, 20nm, 16nm, and below) and implant layers, in particular for process nodes with double patterning and FINFETs. These rules also impose EDGETYPE spacing constraints among cells that must be considered. New approaches are needed to overcome these challenges. These may include more accurate global routing models with tighter coupling to placement, pin access modeling, and better cell library characterization for routing congestion mitigation. Furthermore, as described in recent routability studies, [1] and [2], there can be a great disparity in quality between global and detailed routes for a given placement. In addition to the growing design rule complexities with smaller node sizes, the miscorrelation between global and detailed routes motivates us to use detailed routing as a final arbiter of a given placement’s quality. A new placement benchmark suite will be released to spur development in this area. The benchmark designs will be in Verilog and the version 5.7 Library Exchange Format (LEF) and Design Exchange format (DEF). In addition, a C++ API to the NCTUgr global router ([3] and [4]) will be provided for teams interested in incorporating it into their placement and routing code. More details on downloading this API will be available on the ISPD website. Benchmark suite: We will provide a benchmark suite using the Library Exchange Format (LEF) and Design Exchange format (DEF) 5.7 exchange format for this contest. You can find complete descriptions of these standard ASCII formats at http://www.si2.org/openeda.si2.org/projects/lefdef. For each design, we will provide four files: Cells.lef - Physical characteristics of the technology library for the standard cell library, macros, and IO cells, etc. Tech.lef - Physical characteristics of the routing layers, vias, placement site types, etc. Design.def - Design-specific logical and physical information that represent of the design during any stage of the physical design process. This includes net-list connectivity, grouping information, physical constraints, cell locations and orientations, routing geometry data, etc. Design.v - A Verilog description file of the design. We will provide a sample benchmark suite by October 25, 2013, to help you iron out parsing the data and initially test your tools. We will provide the final benchmark suite by December 11, 2013. Both will be downloadable from the ISPD contest website. LEF/DEF parsers: We strongly encourage downloading the LEF/DEF parsers already available from http://www.si2.org/openeda.si2.org/projects/lefdef. If you do not have an SI2 license, please contact your university staff to obtain a free license for academic use. You may also write your own LEF/DEF parsers if you wish. However, using the already available parsers may save you a considerable amount of effort and time. Contest procedure: Each team will do the following: 1. Create a contest web account. Details will be provided by November 20, 2013. 2. Write a placer/router tool that interfaces with a LEF/DEF parser. 3. For each design, do the following: a. Read the LEF/DEF/Verilog input files. b. Generate a DEF file with all cell instances placed. c. Upload the DEF file to the contest website. Your placement will be routed using the Mentor Graphics Olympus global and detailed routers. This execution will not be visible to the contestants.  Rather, they will get a report of overflows, DRC's, and images. The report will contain the following information: * total wire length, * number of DRC errors, * the location of each DRC error, * detailed information regarding nets involved with each DRC error Notes: 3.1 The cells in the netlist must remain the same. That is, no cell resizing, no addition/deletion of buffers, tech remapping, etc. are allowed. 3.2 The will be limits on how many jobs each team will be allowed to submit per unit time. More details on this restriction will be published on this website with the release of the final benchmark suite. Evaluation metric criteria: Executable submissions will be ranked based upon the following two criteria: 1. Detailed routing quality for the generated placements as evaluated by the Mentor Graphics Olympus detailed router. 2. Placer run-time (multi-core implementations are encouraged). The exact evaluation metric will be published on the website with the release of final benchmark suite. Redhat-6.0 executables will need to be provided for this evaluation. In addition, there will be additional “blind” testing of the final executables for each team on a similar set of unseen benchmark designs. The Prize: There will be monetary prizes awarded to the top 3 teams. More details on this will be announced on the web site. Relevant contest dates: Please make note of the following dates: * The ISPD symposium will be held during March 30 – April 2, 2014. * The contest will be held just prior to the symposium. * The contest will officially start on October 25, 2013. * To test your tools, a sample benchmark suite in LEF/DEF 5.7 exchange data format will be provided by October 25, 2013. Teams are encouraged to download LEF/DEF parsers from http://www.si2.org/openeda.si2.org/projects/lefdef. This requires registering for a free license from the SI2 organization (please visit www.si2.org). * The web-interface details will be provided by November 20, 2013. * To participate, contestants must register by January 15, 2014. Please see the ISPD contest website, http://www.ispd.cc/contests/14/ispd2014_contest.html, for further details. * Benchmark suite-1 will be released by December 15, 2013, and benchmark suite-2 by January 10, 2014. Further details on the benchmark suite. * The contestants must submit an alpha binary submission by February 15, 2014, else be disqualified from the contest. * Each team must also make an alpha binary submission for a compatibility test by February 15, 2014. * The contestants will be required to make their final executable submissions by March 3, 2014. * The contest results will announced during the symposium. Contest registration: * For registration and contest related inquiries, please send e-mails to the following address: ispd2014contest@gmail.com. * Please add "ISPD2014" to the subject line of any email. * To register your team, please provide the following information: 1. Affiliation of the team/contestant(s) 2. Names of team members 3. One correspondence e-mail address for the team Contest organizers: Vladimir Yutsis, Mentor Graphics Corporation David Chinnery, Mentor Graphics Corporation Joseph Shinnerl, Mentor Graphics Corporation Clive Ellis, Mentor Graphics Corporation Igor Gambarin, Mentor Graphics Corporation Wen-Hao Liu, National Tsing Hua University Ismail Bustany (Contest Chair), Mentor Graphics Corporation Bibliography: 1. H. Shojaei, A. Davoodi, and J. Linderoth, "Planning for local net congestion in global routing", ISPD 2013, pp. 85-92, March 2013. 2. Wen-Hao Liu, Cheng-Kok Koh, Yih-Lang Li, “Case study for placement solutions in ISPD11 and DAC12 routability-driven placement contests.” ISPD 2013, pp. 114-119 March 2013. 3. Ke-Ren Dai, Wen-Hao Liu and Yih-Lang Li, "NCTU-GR: Efficient Simulated Evolution Based Rerouting and Congestion-Relaxed Layer Assignment on 3-D Global Routing," IEEE Transactions on Very Large Scale Integration Systems, 2012. (TVLSI) 4. Wen-Hao Liu, Wei-Chun Kao, Yih-Lang Li, and Kai-Yuan Chao, “NCTU-GR 2.0: Multi-Threaded Collision-Aware Global Routing with Bounded-Length Maze Routing”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 709-722, May 2013. 5