ISPD 2016 : Routability-Driven FPGA Placement Contest

Vivado Evaluation Flow

  • Click here for instructions to use Vivado evaluation flow.

Evaluation & Ranking

  • For each design in the benchmark suite, the placers will be ranked based on the contest evaluation metric. The final rank for a placer will be the sum of the individual ranks on all the circuits. The placer with the smallest total rank wins the contest.
  • The placement runtime must be 12 hours or shorter;
  • The placement must be legal, meeting both slice legalization rule and clock legalization rule;
  • The placement has to be routed by Vivado router, and the router has to complete the job within 12 hours. Routing is regarded as failed if it takes more than 12 hours to complete;
  • Score = Routed-WL * (1 + Runtime_Factor)
    • Vivado router reports total routed wirelength. This is the base of the score.
    • Total placement and routing runtime will be used in computing P&R_Runtime_Factor;
    • Runtime_Factor = - (Runtime - Median_Runtime) / 10.0 There is 1% scaling factor for every 10% runtime reduction/addition against the median runtime of all place+route solutions;
    • Runtime factor is between -10% and +10%
  • The failed place/route job will get the lowest rank on this design. In the presence of multiple failures, the break-tie factors are (in order): placer failure, logic legalization failure, clock legalizaiton failure, router failure