ISPD 2018 Contest on Initial Detailed Routing

Announcement

12/6/2017Contest schedule updated.
11/1/2017FAQ updated.
10/1/2017Contest topic announced.

Introduction

Detailed routing can be divided into two steps. First, an initial detailed routing step is used to generate a detailed routing solution while handling the major design rules. Then a detailed routing refinement is performed to fix the remaining design rule violations. This proposed contest focuses on the initial detailed routing step.

Assuming that a global routing result is already well optimized for certain metrics (e.g., timing), a detailed router needs to honor the global routing result as much as possible. In this way, the optimized metrics are kept meanwhile avoids design rule violations. For example, Fig. 1(a) shows a global routing result for a net with a source pin A and sink pins B, C, and D. Because the path from A to B is timing critical, a global router identifies a short path from A to B. However, the path passes a local wiring congestion region which is not seen by the global router. If the detailed router routes wires over that region as shown in Fig. 1 (b), it will have design rule violations. Fig. 1 (c) shows a routing result without short/spacing violations but it will have timing degradation for the path from A to B. On the other hand, Fig. 1 (d) shows a desired solution.


Fig. 1

To minimize the disturbance for net topology, initial detailed routing plays an important role. If the initial detailed routing result can meet the most common routing rules even it is not fully DRC clean, the later detailed routing refinement will have less chance to largely disturb the routing results.

Problem Formulation

Input:

  1. A set of nets with given pins
  2. One or more pin shapes for each pin
  3. Via library with multiple via types for each layer
  4. Global-routing guide for each net
  5. Routing blockages
  6. Track structure for each layer

Design rules:

  1. Open
  2. Short
  3. Min spacing rule
  4. End-of-line spacing rule
  5. Cut-to-cut spacing rule
  6. Min-area rule

Output:

A set of connected wire segments and vias for each net

Objective:

Minimize the following metrics (the exact scoring metric will be announced later)

  1. Short and spacing violations between wires and routing blockages
  2. Short and spacing violations between wires
  3. Min-area rule violation
  4. Off-track / wrong-way wirelength
  5. Global-routing guide violations (total wirelength out of the given guides)
  6. Wirelength and via count
  7. Runtime

Benchmarks

To be announced soon

Submission

To be announced soon

Schedule

November 01, 2017Contest topic announced.
December 15, 2017Sample benchmark suite released.
December 20, 2017Deadline for contest registration.
December 31, 2017Benchmark suite released.
February 15, 2018Deadline to receive alpha router executable submissions from all teams.
March 10, 2018Deadline to receive final router executable submissions from all teams at 11:59pm (PST).
March 25-28, 2018Contest results will be announced at the symposium.

Registration

For registration, please send an email to ispd2018contest@gmail.com including the following information:

Contest Organizers

Wen-Hao Liu Cadence Design Systems
Stefanus MantikCadence Design Systems
William Chow Cadence Design Systems
Gracieli PosserCadence Design Systems
Yixiao Ding Cadence Design Systems

FAQ

  1. Q: Will global routing input be provided?

    A: Yes. Global routing results will be provided by Cadence's tool.

  2. Q: Can we apply track assignment technique for this contest?

    A: Yes. It is welcomed to have track assignment stage.

Contact

For registration or inquiry, please send emails to ispd2018contest@gmail.com.