Announcementsback to top ▲

1/17/2018Evaluation program is updated to fix the multi-cut via counting issues.
1/11/2018Evaluation program is updated to fix the library linkage issues.
12/15/2018Released the evaluation program. Please refer to the README file for instruction.
12/1/2018Released 4 benchmarks (test1-4, 6).
10/15/2018Released 4 sample benchmarks.
10/15/2018Problem Introduction and Tutorial for the ISPD 2019 Contest
09/23/2018Contest topic announced.
12/10/2018Registration deadline.

Abstractback to top ▲

The 2019 ISPD contest augments the 2018 ISPD initial detailed routing contest by adding more realistic design rule settings faced by physical design practitioners in the industry.

Detailed routing can be divided into two steps. First, an initial detailed routing step is used to generate a detailed routing solution while handling the major design rules. Then a detailed routing refinement is performed to fix the remaining design rule violations. This proposed contest focuses on the initial detailed routing step.

Assuming that a global routing result is already well optimized for certain metrics (e.g., timing), a detailed router needs to honor the global routing result as much as possible. In this way, the optimized metrics are kept meanwhile avoids design rule violations. For example, Fig. 1(a) shows a global routing result for a net with a source pin A and sink pins B, C, and D. Because the path from A to B is timing critical, a global router identifies a short path from A to B. However, the path passes a local wiring congestion region which is not seen by the global router. If the detailed router routes wires over that region as shown in Fig. 1 (b), it will have design rule violations. Fig. 1 (c) shows a routing result without short/spacing violations but it will have timing degradation for the path from A to B. On the other hand, Fig. 1 (d) shows a desired solution.


Fig. 1

To minimize the disturbance for net topology, initial detailed routing plays an important role. If the initial detailed routing result can meet the most common routing rules even it is not fully DRC clean, the later detailed routing refinement will have less chance to largely disturb the routing results.

Benchmarksback to top ▲

You can find the first released testcase for the contest, that is a sample benchmark, in the below link:

Instruction to Setup the Development Environment for the ISPD 2019 Contest

A tutorial is also published in the same link.

Benchmark Version #std #blk #net #pin #Layer Die size Tech. node Comments
ispd19_sample 1 22 0 11 0 9 0.017x0.01mm2 45nm This sample testcase is used for the tutorial purpose.
ispd19_sample2 1 22 1 16 0 9 0.017x0.01mm2 45nm This sample testcase has a block and nets connecting to the block.
ispd19_sample3 1 5 1 7 5 16 1.90x2.00mm2 45nm This sample testcase has IO pins, large die size and more metal layers.
ispd19_sample4 2 67 0 22 0 9 0.195x0.195mm2 32nm This sample testcase has special PG nets and all the rules considered in the contest.
ispd19_test1 1 8879 0 3153 0 9 0.1484x0.146mm2 32nm This testcase has special PG nets and all the rules considered in the contest.
ispd19_test2 1 72094 4 72410 1211 9 0.8728x0.5892mm2 32nm This testcase has special PG nets and all the rules considered in the contest.
ispd19_test3 1 8283 4 8953 57 9 0.1953x0.195mm2 32nm This testcase has special PG nets and all the rules considered in the contest.
ispd19_test6 1 179881 16 179863 1211 9 1.3582x1.32544mm2 32nm This testcase has special PG nets and all the rules considered in the contest.

Update history:

    12/1/2018 - Updated ispd19_test1-4,6
    10/20/2018 - Updated ispd19_sample4
    10/15/2018 - Released the sample benchmarks.

Evaluationback to top ▲

Downloads:

Evaluation kit (latest update: 12/15/2018 , version: 1)
Evaluation metric and ranking method (latest update: 12/15/2018)

Evaluation kit includes:
README - instruction of running evaluation
ispd19eval.sh - evaluation script
ispd19eval.tcl - supporting script for Innovus for design rules and connectivity checking
ispd19eval - evaluation binary for guide and track obedience checking and score calculation
ispd19eval.w - weights information for score calculation

Evaluation Script (ispd19eval.sh)

The evaluation script manages the whole evaluation process. It performs the following tasks:

  1. Starts Innovus to perform design rule and connectivity checking.
  2. Generates design rule violation and connectivity reports.
  3. Starts evaluation program to perform guide and track obedience checking, read the Innovus reports, and calculate the final score.
  4. Generates the score table as output.

Usage:
./ispd19eval.sh -lef <input LEF> -guide <input guide> -def <solution DEF> [-keep]

-lef : the input LEF file
-guide : the input route guide file
-def : the routed DEF file
-keep : when it is specified, the intermediate files (logs, reports, scripts, etc.) will not be cleaned after evaluation.

Example:
./ispd19eval.sh -lef sample/ispd19_sample.input.lef -guide sample/ispd19_sample.input.guide -def sample/ispd19_sample.output.def

Evaluation Program (optional)

If you already have design rule and connectivity reports generated by Innovus. You could use the evaluation program directly without using the evaluation script.

Usage:
./ispd19eval -lef <input LEF> -def <solution DEF> -guide <input guide> -georpt <design rule violation report> -conrpt <connectivity report>

-lef : the input LEF file
-guide : the input route guide file
-def : the routed DEF file
-georpt : the design rule violation report generated by Innovus
-conrpt : the connectivity report generated by Innovus

Submissionback to top ▲

To be anounced soon.

Scheduleback to top ▲

September 23, 2018Contest topic announced.
October 15, 2018Sample benchmark suite release.
December 01, 2018Benchmark suite release.
December 10, 2018Deadline for contest registration.
December 15, 2018Details about evaluation metrics and evaluator release.
February 12, 2019Deadline to receive alpha router executable submissions from all teams.
March 01, 2019Deadline to receive beta router executable submissions from all teams.
March 17, 2019Deadline to receive final router executable submissions from all teams at 2:00pm (PST).
April 14-17, 2019Contest results will be announced at the symposium.

Registrationback to top ▲

Deadline: December 10, 2018.

For registration, please send a completed Registration Form to ispd2019contest@gmail.com

Contest Organizersback to top ▲

Gracieli PosserCadence
Wen-Hao Liu Cadence
Stefanus MantikCadence
William Chow Cadence
Yixiao Ding Cadence
Amin Farshidi Cadence

FAQback to top ▲

Please refer to the 2018 ISPD Contest FAQ in the below link:

ISPD 2018 Contest FAQ

Your question may be already answered there. If not, please contact us ispd2019contest@gmail.com.

  1. Q: Can we assume that every net has a global routing guide?

    A: Yes..

  2. Q: Can guide have DRC violation?

    A: Yes. Guide sometimes may have some DRC violation. You may need to violate the guide to resolve the violation.

  3. Q: Can guide have off track via?

    A: Yes. Off track via and wire can be expected in the guides. Some pins may be off track and need off track via and wire to access them.

  4. Q: Is it OK to use patch metals to fix same-net min spacing violations?

    A: Yes, you can.

  5. Q: How patch metals influence in the score? They are included in the wire length penalty? If so, the length of a patch wire is its maximum x-y length?

    A: The patch metals are not included in the wire length. However, you need to be aware that by adding patch metal to solve same-net spacing violation, you will eventually increase the effective metal width on that area. Thus, the required spacing from that patch to other metal will be larger which may introduce new diff-net spacing violations.

  6. Q: In ISPD_2019_test3, there is a layer named OVERLAP, and there are several obstructions using this layer. Can we assume that we don't need to consider any of this information?

    A: Yes. That’s the top-most layer and you’re not supposed to route on that layer anyway. So, any object on that layer can be ignored.

  7. Q: A parallel-run spacing violation is observed in ispd18_test1 (shown in the following figure). We are confused why it is regarded as a parallel-run spacing violation. We are using the test case as well as the evaluator for ISPD'18 (not ISPD'19), so there is no considering for corner-to-corner violation. The description of this violation from Innovus is as follows.

    ======

    Regular Via of Net net554 & Pin of Cell inst5025

    Actual: 0.098 Min: 0.1 Type: ParallelRun

    bbox = (126.335, 106.530) (126.375, 106.620)

    ======


    What are the two parallel edges that causes this parallel-run violation? Should the two edges have positive parallel-run length (i.e., has some overlap either in X direction or in Y direction)?

    A: In this case, the spacing is a corner-to-corner spacing with negative PRL (i.e., no projection overlap).

  8. Q: The example of corner-to-corner in below figure, the spacing rule and 0.15 is used as the wire width. Is this 0.15 horizontal rectangle on the same layer or different layer?


    A: In this example, all the wires are on the same layer. And in this contest, all the rules are applied to the metal on the same layer.

Contactback to top ▲

For registration or inquiry, please send emails to ispd2019contest@gmail.com.