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2010 International Symposium on Physical Design Sponsored by ACM/SIGDA with Technical Co-Sponsorship from IEEE CAS |
PROGRAM Each regular paper presentation runs 25 minutes. Each invited talk is 30 minutes. SUNDAY, March 14 5:30 - 7:00 pm Evening Reception MONDAY, March 15 8:30 - 9:40 am Welcome and Keynote Address (Keynote Talk) Physical Design of Biological Systems 9:40 - 10:10 am Morning Break 10:10 am - 12:10 pm Session 1: Modern Physical Design Challenges (Invited Talk) Going with the Flow: Bridging the Gap between Theory and Practice in Physical Design (Invited talk) Design Planning Trends and Challenges (Invited talk) Physical Design Challenges beyond the 22nm Node (Invited talk) Challenges and Opportunities in Optimization of Automotive Electronics 12:10 - 2:00 pm Lunch 2:00 - 4:15 pm Session 2: Advances in Routing (Invited talk) What Makes a Design Difficult to Route FOARS: FLUTE Based Obstacle-Avoiding Rectilinear Steiner Tree Construction Completing High-Quality Global Routes (Invited talk) Thinking Outside of the Chip B-Escape: A Simultaneous Escape Routing Algorithm Based on Boundary Routing 4:15 - 4:45 pm Afternoon Break 4:45 - 6:10 pm Session 3: Analog Design Automation (Invited talk) Analog Layout Synthesis: What's Missing? (Invited talk) Design Platform for Electrical and Physical Co-Design of Analog Circuits Automatic Generation of Hierarchical Placement Rules for Analog Integrated Circuits 6:10 - 9:00 pm: Dinner Banquet |
TUESDAY, March 16 8:30 - 10:25 am Session 4: Physical Design for 3D ICs (Invited talk) Adding a New Dimension to Physical Design (Invited talk) Physical Design Implementation for 3D IC: Methodology and Tools (Invited talk) Efficient Design Practices for Thermal Management of a TSV Based 3D IC System An Analytical Placer for Mixed-Size 3D Placement 10:25 - 10:55 am Morning Break 10:55 am - 12:35 pm: Session 5: Physical Synthesis Logical and Physical Restructuring of Fan-In Trees Ultra-Fast Interconnect Driven Cell Cloning for Minimizing Critical Path Delay ITOP: Integrating Timing Optimization within Placement Physical Synthesis of Bus Matrix for High Bandwidth Low Power On-Chip Communications 12:35 - 2:00 pm Lunch 2:00 - 3:40 pm Session 6: Design for Manufacturing Dummy Fill Optimization for Enhanced Manufacturability Density Gradient Minimization with Coupling-Constrained Dummy Fill for CMP Control Total Sensitivity Based DFM Optimization of Standard Library Cells A Matching Based Decomposer for Double Patterning Lithography 3:40 - 4:10 pm Afternoon Break 4:10 - 5:40 pm Session 7: Advances in Clock Tree Designs and ISPD'10 Clock Tree Synthesis Contest Skew Management of NBTI Impacted Gated Clock Trees Accurate Clock Mesh Sizing via Sequential Quadratic Programming (Invited talk) ISPD 2010 High Performance Clock Network Synthesis Contest: Benchmark Suite and Results 6:00 - 9:00 pm: Dinner Banquet WEDNESDAY, March 17 8:30 - 10:40 am Session 8: Performance and Reliability Optimization (Invited talk) Impact of Local Interconnects on Timing and Power in a High Performance Microprocessor Interconnect Power and Delay Optimization by Dynamic Programming in Gridded Design Rules Performance Study of VeSFET-Based, High-Density Regular Circuits A Statistical Framework for Designing On-Chip Thermal Sensing Infrastructure in Nano-Scale Systems Optimal Wiring Topology for Electromigration Avoidance Considering Multiple Layers and Obstacles 10:40 - 11:10 am Morning Break 11:10 am - 12:25 pm Session 9: Clustering and Biochip Placement & Routing SafeChoice: A Novel Clustering Algorithm for Wirelength-Driven Placement Droplet-Routing-Aware Module Placement for Cross-Referencing Biochips A Two-Stage ILP-Based Droplet Routing Algorithm for Pin-Constrained Digital Microfluidic Biochips 12:25 - 12:40 pm Closing Remarks 12:40 - 2:00 pm Lunch |