ISPD 2016 : Routability-Driven FPGA Placement Contest

FAQ

  • General

    1. Is parallel computing allowed? Can I submit Windows binary?
      No. Only single-thread executable linux-64 is allowed in this contest.
    2. What is suggested command-line to run the placer?
      PlacerName -aux design.aux -out design_placed.pl
    3. What kind of the output format should the placer produce?
      Please see "Bookshelf Format for FPGA Placement" below.
    4. Is there any routing information provided like number of tracks?
      Routing information is not provided. Participants can read Xilinx manuals to understand FPGA routing architecture.
    5. Do I have to submit source code ?
      No you don't have to submit source code. You do need to submit a binary executable on Linux (statically linked preferred). Please submit your alpha version by Feb 15th. The orginizer will need to verify that your binary can be run on testing environment.


  • Benchmarks

    1. We were wondering if you could you explain more about the format of IOs in the benchmarks? For example, for FPGA-example1, how many IOs are available and how many of them are allocated?
      All the IOs of the benchmark should be placed/fixed. IOs include: IBUF/OBUF/BUFG


  • Vivado Evaluation Flow

    1. Can we get the integration flow with Vivado?
      Yes Vivado integration flow has been released. The users will need to apply licenses, download Vivado 2015.4 and a special patch to have the integration flow.
    2. Can I get the second Vivado license?
      Yes you can get multiple Vivado licenses.


  • Legalization

    1. Please check Legalization Rule for detailed information.


  • Bookshelf Format for FPGA Placement:

    1. Library cell (.lib file):
      • Each instance has a corresponding master library cell. It is defined in nodes file.
      • All library cells are defined in design.lib, a new addition to bookshelf format.
    2. PIN:
      • All pins are defined in library file (.lib) cell section.
      • Each instance has the same number of pins as defined in its master cell.
      • Not all the pins of an instance are used. Some are left unconnected.
      • Library file defines certain attributes associated with pins: direction, clock, and control.
      • Each net is a collection of pins, as specified in nets file.
    3. Layout file (.scl file):
      • Layout file is re-defined to accomodate FPGA placement.
      • There are two section in layout file: site definition section and site map section.
      • SITE definition speicifies available resources (LUT/FF/RAMB/DSP) that can be placed in one site.
      • RESOURCES specifies cell names that correspond to certain resource.
      • SITEMAP specifies the two-dimension array of sites for the entire device/chip.
    4. Placement file (.pl file):
      • The location of an instance has three fields: x-coord, y-coord (to determine the SITE) and BEL (index within the SITE).
      • In released benchmarks, placement file only contains locations of fixed instances (IBUF/OBUF/BUFGCE etc). These instances' locations, including BEL numbers, are not allowed to change during placement.
      • Placer's output placement file should contain locations of all instances
      • The following diagram shows the BEL number for LUTs/FFs placed inside a SLICE SITE:
              ==========================
              |   LUT 15   |   FF 15   |  
              --------------------------
              |   LUT 14   |   FF 14   |  
              --------------------------
              |   LUT 13   |   FF 13   |  
              --------------------------
              |   LUT 12   |   FF 12   |  
              --------------------------
              |   LUT 11   |   FF 11   |  
              --------------------------
              |   LUT 10   |   FF 10   |  
              --------------------------
              |   LUT  9   |   FF  9   |  
              --------------------------
              |   LUT  8   |   FF  8   |  
              --------------------------
              |   LUT  7   |   FF  7   |  
              --------------------------
              |   LUT  6   |   FF  6   |  
              --------------------------
              |   LUT  5   |   FF  5   |  
              --------------------------
              |   LUT  4   |   FF  4   |  
              --------------------------
              |   LUT  3   |   FF  3   |  
              --------------------------
              |   LUT  2   |   FF  2   |  
              --------------------------
              |   LUT  1   |   FF  1   |  
              --------------------------
              |   LUT  0   |   FF  0   |  
              ==========================
        
      • The following is a snippet of a placement file:
              inst_1000 165 161 0                (this instance is a LUT)
              inst_1001 165 161 1                (this instance is a LUT)
              inst_1002 165 161 15               (this instance is a LUT)
              inst_1003 165 161 0                (this instance is a FF)
              inst_1004 165 161 15               (this instance is a FF)
              inst_1100 29 0 0                   (this instance is a DSP)
              inst_1101 29 2 0                   (this instance is a DSP)
              inst_1200 34 0 0                   (this instance is a BRAM)
              inst_1201 34 5 0                   (this instance is a BRAM)