Benchmark Suites

The 2014 ISPD Detail Routing-Driven Placement Contest uses realistic benchmarks to evaluate all the contest submissions. We shall provide a benchmark suite using the 5.7 Library Exchange Format (LEF) and Design Exchange format (DEF) along Verilog descriptions for each benchmark design. You can find complete descriptions of these standard ASCII LEF/DEF formats at http://www.si2.org. For each design, we shall provide four files:

cells.lef - Physical characteristics of the technology library for the standard cell library, macros, and IO cells, etc.
tech.lef - Physical characteristics of the routing layers, vias, placement site types, etc.
floorplan.def - Design-specific logical and physical information that represent of the design during any stage of the physical design process. This includes net-list connectivity, grouping information, physical constraints, cell locations and orientations, routing geometry data, etc.
design.v - A Verilog description file of the design.

The sample benchmark suite has been published on October 25, 2013 to help you iron out parsing the data and initially test your tools. You may download the sample benchmark suite from here.

Please cite the following paper when you refer to these benchmarks in a publication:
Vladimir Yutsis, Ismail S. Bustany, David Chinnery, Joseph Shinnerl, and Wen-Hao Liu, "ISPD 2014 Benchmarks with Sub-45nm Technology Rules for Detailed-Routing-Driven Placement," Proceedings of ACM International Symposium on Physical Design, pp. [TBD], 2014.