ISPD 2014 Detailed Routing-Driven Placement Contest
[Evaluation and Ranking]
[Q & A]
Q & A
Questions regarding the PG grid for Benchmark Suite A:
Question 1: The topology of PG rails depicted in the floorplan.def of design "mgc_des_perf_1" crosses metal1 to metal5. Should we also have to consider the overlaps between PG rails and pins in the metal layers (such as metal1) other than metal2?
Please refer to Figure 1 and Figure 2 as a reference to complement this answer.
The signal pins and relevant PG layers have the following characteristics in Benchmark Suite A:
The signal pins for the standard cells are on metal1 and metal2 layer only.
There are no PG pins within standard cells.
There are horizontal PG rails on the metal1 and metal3 layers and vertical PG stripes on the metal2 layer.
No routing is allowed on metal1 layer.
As a result, the following restrictions in terms of pin reachability and DRC correctness should be observed by placer:
You cannot have metal2 pins overlapping with metal2 stripes. i.e., All the metal2 pins should be separated from the metal2 vertical stripes by an appropriate spacing (defined from the wide metal spacing rules on metal2 layer) because of shorting and DRC violations.
You cannot have metal1 pins placed under metal2 stripes because these pins will not be reachable since the metal1 layer is not a routable layer.
More complicated pin shapes, e.g. an L-shaped pin, could be placed partially under a metal stripe and remain reachable.
Some metal2 pins can be placed under metal3 stripes. In such cases, the placer should be able to recognize short connections on the metal2 layer and DRC reachability errors for these pins taking into consideration extra spacing next to the wider metal3 stripe (3.5um). A conservative approach would be to prevent overlap between metal2 pins and metal3 horizontal stripes.
With the exception of metal1 and metal2 layers no other pins versus PG stripes overlaps need to be considered.
Question 2: Because the area of a via used for the PG rails may exceed the area of a PG rail connected to the via, should we have to consider the overlaps between such vias and the module pins?
No. All the vias used for PG rails are enclosed by PG stripes/rails completely.
Question 3: According to the benchmark description document, should we only have to consider the following two situations for PG rails?
Metal1 pins under metal2 power stripes are not accessible by vias.
Metal2 pins cannot overlap metal2 stripe.
Please see the answer to question 1.
Figure 1: Sample power and ground Metal3 Stripes from a Benchmark Suite A design
Figure 2: Sample power and ground vias and cell pins from a Benchmark Suite A design
Question 4: Would the edge of a standard cells be the EDGETYPE other than 1 or 2?
No, the specified edge types are either 1 or 2.
Question 5: We found that the width of metal2 PG rails are quite small compared
with the chip width (e.g. 0.51um/722um for "mgc_edit_dist_1"). Would
the width of PG rails in the final test cases change a lot compared
Yes, the edge width of the PG rails, impose NDR's, pin geometries, assignment of edge types may be different
for some of the designs in the blind benchmark suite. However, no new design rules will be introduced.
Questions regarding the non-default routing rule (NDR) for Benchmark Suite A
Question 1: For NDRs with double wire width and double wire spacing defined in floorplan.def as follows:
*Description in the floorplan.def file of mgc_des_perf_1*
+ LAYER metal1 WIDTH 100 SPACING 100
+ LAYER metal2 WIDTH 200 SPACING 150
+ LAYER metal3 WIDTH 200 SPACING 150
+ LAYER metal4 WIDTH 200 SPACING 150
+ LAYER metal5 WIDTH 100 SPACING 100
+ VIA VIA34_2cut_W
+ VIA VIA23_2cut_E
+ VIA VIA23_2cut_N
+ VIA VIA23_2cut_S
+ VIA VIA34_2cut_N
+ VIA VIA23_2cut_W ;
+ LAYER metal1 WIDTH 100 SPACING 100
+ LAYER metal2 WIDTH 100 SPACING 100
+ LAYER metal3 WIDTH 200 SPACING 200
+ LAYER metal4 WIDTH 200 SPACING 200
+ LAYER metal5 WIDTH 200 SPACING 200 ;
Are the following explanations correct?
A. The statement "+ VIA VIA34_2cut_W" means that EM_NDR is applied to the nets connecting to VIA34_2cut_W.
Yes. The six vias defined within the "EM_NDR" section above are preferred vias for all the net assigned to that NDR. Note that NDRs are preferred (i.e. not required) rules. The detail routing may decide to use regular vias (so called taper vias) for particular small connections, but at much higher cost.
B. The statement "+ LAYER metal1 WIDTH 100 SPACING 100" means that if a net described in A is routed in metal1, a minimum width of 0.1um and a minimum spacing of 0.1um are required.
Yes. Please remember that metal1 routing is prohibited for the designs in Benchmark Suite A because of the routing blockage imposed on the metal1 layer. In effect, these NDRs only apply to the higher metal layers.
C. The statement "+ LAYER metal1 WIDTH 100 SPACING 100" means that if DWDS is applied to a net which is routed in metal1, a minimum width of 0.1um and a minimum spacing of 0.1um are required.
Yes. Again, because of the routing blockage on the metal1 layer, these NDRs only apply to the higher metal layers.
Questions regarding DEF Placement submission errors.
Question 1: I am getting a parser error when I submit my DEF file.
Due to an error in the parsing script, please make sure that you match the spacings in the COMPONENTS section of your submitted DEF
placement file to the spacings in the COMPONENTS section in the floorplan.def file. One common COMPONENTS transcription error,
is to alter the spacings. For instance, writing
+ PLACED (157000 128000) N;
+ PLACED (157000 128000) N ;
Questions regarding submitting the placer executable binary
Question 1: What are the instructions for submitting the placer executable?
Name your executable "placer"
Upload a gzipped verison, i.e. placer.gz, to the "to_ISPD_contest" folder in your support-net account
The executable should have the following required arguments:
-tech_lef -- specifies the tech.lef input file
-cell_lef -- specifies the cell.lef input file
-floorplan_def -- specifies the floorplan.lef input file
-verilog -- specifies the design.v input file
-output -- specifies the output placement DEF file
It may also have the following optional argument:
-cpu -- specifies the number of CPU's to use
- An example for running your command:
placer -tech_lef tech.lef -cell_lef cell.lef -floorplan_def floorplan.def -verilog design.v -cpu 4 -output placed.def