Announcements

March 6, 2014:
The final deadline has been extended to 11:59pm Mrach 16th (California time).
March 6, 2014:
1. The computing grid will be down from Friday 7pm - Saturday 8pm (California time) this weekend for maintenance. Please note that jobs submitted late Friday afternoon may not finish in time for feedback.
2. We apologize for this loss computing time, and accordingly shall extend the contest deadline by two days to midnight March 15th (California time).
3. Several of you have asked about the submission process for the executable binaries. The process is similar to that we used for submitting the alpha binaries with a minor change in the name of one of the required arguments. That is,
  - Name your executable "placer"
  - Upload a gzipped verison, i.e. placer.gz, to the "to_ispd_contest" folder in your support-net account
  - The executable should have the following required arguments:
  - It may also have the following optional argument:
    
    -cpu -- specifies the number of CPU's to use
  - An example for running your command:
    
    placer -tech_lef tech.lef -cells_lef cells.lef -floorplan_def floorplan.def -verilog design.v -cpu 4
February 25, 2014: An updated version of NCTUgr has been released. It contains a bug fix. NCTUgr provides a function called "getPassingNet" that can query a G-edge to return a set of nets passing through the G-edge. However, in some corner cases, getPassingNet does not correctly report all the nets passing through the G-edge (i.e. some nets are missed) The bug is fixed. Also, Furthermore, the run time complexity of getPassingNet has been reduced. Originally, its time complexity is O(N), where N is the number of all nets. In the updated version, its time complexity becomes O(ne), where ne denotes the number of the nets passing through the queried g-edge. In the attached package, three files have been updated.
1. Router.a
2. README.pdf
3. header/GlobalRouter.h
For more questions regarding NCTUgr, please contact its author, Dr. Wen-Hao Liu (dnoldnol@gmail.com).

February 17, 2014:
- We have updated Benchmark Suite B to fix the ROW definition in the floorplan.def.
- We have posted the instructions to submit your placer alpha executable binary. Please see the submission section for the details; Please remember to submit your alpha binary executable by February 20, 2014. Failure to do so, will disqualify you from the contest. Please visit the submissions information section to learn about the requirements for the submitted binary executable.
February 13, 2014:
We have added a question and answer (Q & A) section to this webpage. Please visit it to see answers to questions from contestants.
February 11, 2014:
We have extended all upcoming deadlines by three days to compensate for the lost computing time last weekend. The next deadline is on February 20th to submit a test executable. Please see the schedule for upcoming deadlines. Please note that failure to submit a test executable by that deadline will disqualify you from the contest.
February 04, 2014:
- Benchmark Suite B has been released. You may download it here. Please note that the size of this gzipped tar file is about 96 MBs. Please email us if you have a problem downloading it.
- Suite B consists of three designs adapted from benchmarks released by IBM Corporation for the DAC 2012 placement contest. In contrast to the test cases in Suite A, the test cases in Suite B have many fixed macros and hence a more complicated floorplan geometry; There are numerous modifications to the original benchmark. Among them are (1) a technology LEF description that is based on 28nm technology nodes, (2) a power/ground grid, (3) various design rules, (4) I/O pin adjustments, and (5) various standard cell pin modifications and location adjustments to ensure valid electrical rules.
- A detailed description of this benchmark will be e-mailed to the team leads today. Since it is copyrighted material, please do not share the emailed document with anyone outside your team until it is officially published in the 2014 ISPD Proceedings.
- Please note that you MUST download an updated version of the DEF placement file checker that is compatible with Benchmkark Suite B. As before note that no Verilog input is required. If you wish to compare DEF versus Verilog, you will need to modify the Verilog-Perl path in the script to point to your local path for the CPAN Verilog module. If you do not have CPAN Verilog, you can download it from http://search.cpan.org/dist/Verilog-Perl/.
February 03, 2014:
Released a C++ API to RippleDP detailed placer from Professor Evangeline F.Y. Young and her Ph.D. student William Chow at the Chinese University of Hong Kong.
January 24, 2014:
- We have discovered a problem with our detailed placement script that can impact the routability of your submitted designs. Please resubmit your placements to get the correct feedback.
- Please make sure to follow contest related announcement and issues at the Google group forum. Also, feel free to post your questions there so that everyone shares the benefit.
January 20, 2014:
- The contest forum is also available on this webpage here.
- We will start publishing the highest benchmark scores on this website. To see the highest scores please click here.
- ispd2014_placement_checker.pl usage note: Please note that no Verilog input is required. If you wish to compare DEF versus Verilog, you will need to modify the Verilog-Perl path in the script to point to your local path for the CPAN Verilog module. If you do not have CPAN Verilog, you can download from http://search.cpan.org/dist/Verilog-Perl/.
January 17, 2014:
- To answer some of the contestants' questions regarding the meaning of the design rules, please refer to the 2009 LEF/DEF version 5.7 Reference manual provided by Cadence Design Systems Inc. and posted on http://www.si2.org/.
- The contest forum is accessible from this webpage.
January 15, 2014:
Released a DEF placement file checker perl script. Please run this script on your to be submitted DEF placement file to ensure it is a valid submission. Please download it from the [Downloads] section. This is a Perl script to verify your placed DEF file versus the provided floorplan DEF. If your placed DEF has errors identified by this script, detailed routing will not be performed on it. Invoke as follows:

ispd2014_placement_checker.pl -floorplan_def floorplan.def.gz -placed_def placed.def.gz
Please note that you will need to update the top line of the file to point to your local version of Perl.
January 14, 2014:
- The release of benchmark suite B will be delayed. We will release it by January 31st or possibly earlier. we shall send and updte on this ASAP. Please be advised that it will be based on the 2012 DAC benchmark suite and a 28nm design rule library.
- Please note that we have discovered a computing server grid problem that caused submitted jobs to wait in the queue for an extended period of time. We have fixed the problem last night. You should see faster response time when you submit your *.def.gz placement files. Please e-mail us feedback to ispd2014contest@gmail.com if you experience any submission issues.
- Thanks for the generous assistance from Professor Evangeline F.Y. Young and her Ph.D. student William Chow at the Chinese University of Hong Kong, we will be releasing an API for her group's detailed placer, RippleDP. Please stay tuned for more on this.
- Thus far, there are 11 registered teams in the contest.
December 21, 2013:
The https://mst.mentorg.com website is now open for DEF placement submissions. Please log in using your Mentor Graphics support-net account to upload your submissions. Please follow the submission procedure instructions provided in the Benchmark Suite A release note.
December 20, 2013:
Benchmark suite A release document has been released. Please download it from the [Downloads] section. We will post a note to indicate when the Support-Net website is open for placement submissions soon.
December 16, 2013:
Benchmark suite A has been released. Please download it from the [Downloads] section. The benchmark release notes will be posted by December 19, 2013.
December 10, 2013:
- Benchmark release date change: We are diversifying the type of benchmark designs used in this contest to reflect a wider sampling of the place-and-route challenges faced today at lower technology nodes. The benchmark suite will include modified verions of designs from the ISPD-2013 benchmark suite (with no macro blocks) and from the DAC-2012 benchmark suite (with macro blocks). We shall release it in two phases (in LEF/DEF) as follows:
  - December 16, 2013: Release date of the modified ISPD-2013 benchmark suite.
  - January 15, 2014: Release date of the modified DAC-2012 benchmark suite.
- Accordingly, we are extending the following deadlines:
  - Contest registration deadline: January 15, 2014 (from December 15, 2013).
  - Deadline for submitting final executables: March 7, 2014 (from February 25, 2014).
December 3, 2013:
- Released a C++ API to the NCTUgr global router (please download from the [Downloads] section).
November 9, 2013:
- Please note that the benchmark suite will be released earlier than previously announced. The new release date for benchmark suite A is December 16, 2013. The release date for benchmark suite B is February 4, 2014. We hope this will give contestants more time to incorporate the data and design rules into their implementations.
October 25, 2013:
- The call for participation in the ISPD 2014 detailed routing-driven placement contest is announced. Please read the file "ISPD_2014_Contest_Details" provided in "Contest Details." It contains the important information regarding the contest.
- The sample benchmark suite in LEF/DEF 5.7 format is released. Please download the file "ISPD_2014_Sample_Benchmark_Suite."
- The contest details are described in ISPD_2014_Contest_Details.pdf or ISPD_2014_Contest_Details.txt.
- We reserve the right to make changes in the contest rules or benchmarks in the future. It is your responsibility to check the contest announcements on this web page until the submission deadline.