ISPD 2017 Contest : Clock-Aware FPGA Placement

FAQ

  • Clocking Specific

    1. Number of global clocks in each clock region is at most 24 clocks
      Within each clock region, each half column has at most 12 clocks
      Is this the complete set of clock routing constraints? meaning that if all of these are satisfied and the placement is legal w.r.t site types, all the clock nets can be routed ? (not considering signal nets)

      Please refer to the Problem Definition page for a set of clock routing rules (for track assignment) to have a routable solution. However, those routing rules are in addition to the challenge definition, and as such, are not neccessary to be satisfied for this challenge.
    2. Suppose there is a half-column with 12 different clocks and the half column immediately next to it (left/right) has another set of 12 different clocks. Can the clocks be routed in this case?
      Yes, the half columns within a clock region can have different clocks.
    3. Each clock region has enough resources to accommodate all clock loads assigned to that region.
      Does this only mean legality with respect to site types or is there some other aspect?

      Yes, this applies to legality with respect to site capacities.
    4. If both distribution and routing networks are segmented as clock regions, then how could a clock tree across more than one clock regions?
      As mentioned distribution and routing networks are segmented at clock region boundaries. This means there are three state buffers at the boundaries to allow a clock to traverse to a neighboring clock region, or to disable the buffer and allow the same track to be used by two clock nets in neighboring clock regions.
    5. So non-clock routing will not use the routing and distribution network resources, right?
      Yes, you can assume signals that are not driven by a BUFGCE do not use routing/distribution resources.
    6. Does the second rule cover the first one? That is, for generating a placement result without violating any clocking constraint, we only need to ensure that for each half column of a clock region, k does not exceed 12, where k is the number of different clock signals of the FFs placed in the half column.
      No. The second rule doesn't cover the first rule. Each clock region has many half columns.
    7. What is the definition of "half column" in the 2nd clocking rule? Could you define the belonging sites of each half column?
      Half column starts from the left mode column of the clock region. There's an upper half column and a lower half column. Every two neighboring upper half columns form a 12-clock rule, starting from the left most. Same for every two lower half columns.


  • General

    1. Is parallel computing allowed? Can I submit Windows binary?
      No. Only single-thread executable linux-64 is allowed in this contest.
    2. Does the Contest provide an ILP solver (such as CPLEX or Gurobi)? If yes, could you tell me the usage for the solver? If no, can we embed an ILP solver in our submitted program?
      No the contest doesn't provide ILP solver. You can use embedded solver in your submitted binary (statically linked).
    3. What is suggested command-line to run the placer?
      PlacerName -aux design.aux -out design_placed.pl
    4. What kind of the output format should the placer produce?
      Please see "Bookshelf Format for FPGA Placement" below.
    5. Is there any routing information provided like number of tracks?
      Routing information is not provided. Participants can read Xilinx manuals to understand FPGA routing architecture.
    6. Do I have to submit source code ?
      No you don't have to submit source code. You do need to submit a binary executable on Linux (statically linked preferred). Please submit your alpha version by Feb 15th. The orginizer will need to verify that your binary can be run on testing environment.


  • Benchmarks

    1. We were wondering if you could you explain more about the format of IOs in the benchmarks? For example, for FPGA-example1, how many IOs are available and how many of them are allocated?
      All the IOs of the benchmark should be placed/fixed. IOs include: IBUF/OBUF/BUFG


  • Vivado Evaluation Flow

    1. Can we get the integration flow with Vivado?
      Yes Vivado integration flow will be released. The users will need to apply licenses, download Vivado 2016.4 and a special patch to have the integration flow.
    2. Can I get the second Vivado license?
      Yes you can get multiple Vivado licenses.


  • Legalization

    1. Please check Legalization Rules document for detailed information.


  • Bookshelf Format for FPGA Placement:

    1. Library cell (.lib file):
      • Each instance has a corresponding master library cell. It is defined in nodes file.
      • All library cells are defined in design.lib, a new addition to bookshelf format.
    2. PIN:
      • All pins are defined in library file (.lib) cell section.
      • Each instance has the same number of pins as defined in its master cell.
      • Not all the pins of an instance are used. Some are left unconnected.
      • Library file defines certain attributes associated with pins: direction, clock, and control.
      • Each net is a collection of pins, as specified in nets file.
    3. Layout file (.scl file):
      • Layout file is re-defined to accomodate FPGA placement.
      • There are two section in layout file: site definition section and site map section.
      • SITE definition speicifies available resources (LUT/FF/RAMB/DSP) that can be placed in one site.
      • RESOURCES specifies cell names that correspond to certain resource.
      • SITEMAP specifies the two-dimension array of sites for the entire device/chip.
    4. Placement file (.pl file):
      • The location of an instance has three fields: x-coord, y-coord (to determine the SITE) and BEL (index within the SITE).
      • In released benchmarks, placement file only contains locations of fixed instances (IBUF/OBUF/BUFGCE etc). These instances' locations, including BEL numbers, are not allowed to change during placement.
      • Placer's output placement file should contain locations of all instances
      • The following diagram shows the BEL number for LUTs/FFs placed inside a SLICE SITE:
              ==========================
              |   LUT 15   |   FF 15   |  
              --------------------------
              |   LUT 14   |   FF 14   |  
              --------------------------
              |   LUT 13   |   FF 13   |  
              --------------------------
              |   LUT 12   |   FF 12   |  
              --------------------------
              |   LUT 11   |   FF 11   |  
              --------------------------
              |   LUT 10   |   FF 10   |  
              --------------------------
              |   LUT  9   |   FF  9   |  
              --------------------------
              |   LUT  8   |   FF  8   |  
              --------------------------
              |   LUT  7   |   FF  7   |  
              --------------------------
              |   LUT  6   |   FF  6   |  
              --------------------------
              |   LUT  5   |   FF  5   |  
              --------------------------
              |   LUT  4   |   FF  4   |  
              --------------------------
              |   LUT  3   |   FF  3   |  
              --------------------------
              |   LUT  2   |   FF  2   |  
              --------------------------
              |   LUT  1   |   FF  1   |  
              --------------------------
              |   LUT  0   |   FF  0   |  
              ==========================
        
      • The following is a snippet of a placement file:
              inst_1000 165 161 0                (this instance is a LUT)
              inst_1001 165 161 1                (this instance is a LUT)
              inst_1002 165 161 15               (this instance is a LUT)
              inst_1003 165 161 0                (this instance is a FF)
              inst_1004 165 161 15               (this instance is a FF)
              inst_1100 29 0 0                   (this instance is a DSP)
              inst_1101 29 2 0                   (this instance is a DSP)
              inst_1200 34 0 0                   (this instance is a BRAM)
              inst_1201 34 5 0                   (this instance is a BRAM)