ISPD 2017 Contest : Clock-Aware FPGA Placement
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March 22, 2017:
Winners were announced at ISPD. Congratulations!
| Ranking |
Team |
Affilication |
| 1st |
UTPlaceF2.0 |
University of Austin Texas |
| 2nd |
NTUfplace |
National Taiwan University |
| 3rd |
RippleFPGA |
Chinese University of Hong Kong |
| 4th |
VDAPlacer |
National Chiao Tung University |
| 5th |
GPlace |
University of Guelph, Canada |
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March 13, 2017:
Thank you for your participation! Benchmarking is completed. The winners will be announced at ISPD.
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March 3, 2017:
FAQ page is updated with latest questions and answers.
February 27, 2017:
One more benchmark is released: it is a harder testcase in terms of clock legalization:
clk_design5 ,
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February 23, 2017:
FAQ page is updated with latest questions and answers.
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February 17, 2017:
Patch_05 is ready to download at GitHub : clock routing issue is fixed.
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February 15, 2017:
Patch_04 is ready to download at GitHub: detailed information for clock legalization rule violation.
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February 15, 2017:
Click here for mapping Vivado reported half column region to Bookshelf coordinates.
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February 14, 2017:
Binary submission schedule:
| Binary |
Date |
Description |
| Alpha |
Feb 15th |
Ensure that binary runs on testing platform. No library dependence issues. |
| Final |
Mar 9th |
Final executable that runs on contest benchmarks.
|
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February 14, 2017:
Please submit your Alpha version placer by email ispd2017contest@gmail.com
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February 14, 2017:
Benchmarks were updated: new clock region parameter "half-column-start-column" added:
README file contains detailed information:
clk_design1 ,
clk_design2 ,
clk_design3 ,
clk_design4
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February 10, 2017:
Vivado patch_03 is ready to download through GitHub.
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February 9, 2017:
Vivado patch_02 is ready to download through GitHub.
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February 9, 2017:
Benchmarks were updated: (1) BUFG location (FIXED); (2) Layout file clock region
clk_design1 ,
clk_design2 ,
clk_design3 ,
clk_design4
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February 3, 2017:
Benchmarks were updated with copyright information added:
clk_design1 ,
clk_design2 ,
clk_design3 ,
clk_design4
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February 3, 2017:
Vivado placement evaluation flow is ready. Click here for instructions. Note that you need to download the full benchmarks for the evaluation flow.
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February 2, 2017:
full benchmarks were updated with design.dcp added:
clk_design1 ,
clk_design2 ,
clk_design3 ,
clk_design4
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January 31, 2017:
4 benchmarks were updated with BRAM clock pin added:
clk_design1 ,
clk_design2 ,
clk_design3 ,
clk_design4
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January 31, 2017:
Evaluation metrics are posted
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January 12, 2017:
Please check FAQ
page for frequently answered questions.
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January 12, 2017:
4 benchmarks were updated:
clk_design1 ,
clk_design2 ,
clk_design3 ,
clk_design4
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January 10, 2017:
More clock-aware placement benchmarks are available:
clk_design1 ,
clk_design2 ,
clk_design3 ,
clk_design4
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December 13, 2016:
ISPD 2016 contest benchmarks are available. Click
here
to download.
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December 13, 2016:
Sample benchmark updated. Download
clk_design1
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December 12, 2016:
First sample benchmark ready. Download
here
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November 22, 2016:
Contest topic announced. Please read the
call for participation
document for details.